The present invention relates to the multiplier and arithmetic logic unit functions for floating point numbers.
Floating point systems typically contain a separate multiplier and arithmetic logic unit (ALU). The multiplier has an exponent portion which adds together the exponents of the two multiplicands and a fraction unit with a multiplying array for multiplying the two fraction portions of the multiplicands together. After the fraction is multiplied, a carry propagate add is performed and the resulting fraction is normalized and rounded. The normalization involves shifting the decimal point to put the fraction in format of 1.XX . . . X. The combined exponent then has a number added to it corresponding to this shift amount to produce the final product.
The arithmetic logic unit can receive two numbers for addition or subtraction, one of which numbers could be the result of a multiply operation. A single multiply operation typically takes two clock cycles and a single addition operation also takes typically two clock cycles. Thus, in order to do a multiply-accumulate operation, four clock cycles are needed.